Apple GPU Compiler Backend Research Engineer, Graphics, Game and ML

In this role, you will have the opportunity to work on defining the roadmap for Apple GPU architecture and unleash the potential for new applications. You will work cross-functionally with several hardware and software teams to prototype compiler feature support, code generation and a slew of optimizations. You will be responsible to evaluate the efficacy of the proposed changes and provide feedback. Your work will have tremendous impact across all Apple devices. We in the GPU compiler team have a strong track record of delivering optimal solutions for Apple Silicon GPUs. We have built synergies with hardware and software teams to explore and implement these solutions from conception, to prototyping to finally productizing and shipping. We strongly believe that being involved from concept allows us to unlock the true potential of new GPU architectures. We are seeking a highly skilled Compiler Backend Research Engineer to join our team. The role involves researching, designing, prototyping and implementing Apple GPU compiler optimizations to improve performance and functionality across all Apple devices. The GPU that you will work on will be shipped in every Apple device with a GPU. You will work on an LLVM-based compiler backend to generate optimized GPU binaries for future Apple Silicon GPUs that run graphics and compute workloads. Minimum Qualifications: Experience with modern C programming BS with 5 years experience, MS or PhD in computer science or related field. Knowledge of GPU architectures and how they differ from CPU architectures Proven industry experience with strong background in compilers Passionate about solving exciting problems related to the state-of-the-art Apple Silicon GPUs Excellent written and verbal communication skills Motivated to build constructive and effective relationships and solve problems collaboratively Preferred Qualifications: Hands-on experience developing LLVM-based compiler backends Experience with instruction selection, instruction schedulers and register allocators for CPU or GPU compiler backends