What are the responsibilities and job description for the Analog IC Design Engineer position at Apple?
At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a visionary and uncommonly talented IC Designer. As a member of our dynamic group, you will have the rare and rewarding opportunity to craft upcoming products that will delight and inspire millions of Apple’s customers every single day.
In this role, the key responsibilities are the following: Involved in specifications of analog portions of IC. Behavioral modeling to validate architectures. Transistor-level feasibility studies for various blocks in ADC/DAC. Crafting blocks and documenting design towards formal design reviews. Drive mask design to implement layout view of designs. Top-level simulations to validate top-level integration. Defining production/bench-level test-plans. Taking lab measurements to validate analog designs. Driving/reviewing yield/lab test results to drive bug fixes. Design for ESD compliance.
Minimum Qualifications:
Bachelor's of Science in Electric Engineering with 10 years of relevant experience preferred
Preferred Qualifications:
Do you have a proven track record of taking chips to production in the following areas?
Deep knowledge of ADC/DAC architectures and knowing which are suitable for given applications
Deep knowledge of band-gaps, bias, op-amps, switched-cap circuits, LDOs, feedback and compensation techniques
Proven expertise in the following areas:
Significant knowledge of low noise design techniques
Significant knowledge of high precision techniques in presence of device mismatch
Experience in C / Matlab / Verilog modeling
Strong device physics knowledge as it applies to analog IC designs
Proven working experience in using spectrum analyzers, oscilloscopes, signal generators, etc. to validate analog designs
Extensive experience working with production test engineers to firm up test plans and design for testability details