What are the responsibilities and job description for the Front-End CAD Methodology Engineer position at Apple, Inc.?
Do you love building elegant solutions to highly complex challenges? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you'll be responsible for crafting and building the technology that fuels Apple's devices. Together, you and your team will enable our customers to do all the things they love with their devices!
As a Front-End Methodology CAD Engineer, you will play a major role in promoting a reliable\nwork environment for developing, maintaining, and improving automation software that design\nteams use for creating, modifying and analyzing RTL. Furthermore, you may support and develop RTL analysis applications like Reset Domain Crossing (RDC), Clock Domain Crossing (CDC), and Lint applications for our SoCs across multiple design sites. In addition, you will have the opportunity to develop Generative AI solutions that the design team can use to improve experience working with these RTL Construction and Analysis applications.\n\nThe Front-End CAD Methodology Engineer plays a key role in promoting and driving robust,\nscalable methodology solutions across RTL Design and DV teams within Apple's HWTech\norganization. You will help ensure the right flows are being used at the right time for project\nmilestones and proper sign-offs are followed through. You will help curate internal training\nmaterials and coordinating vendor trainings so that our Designer/DV engineers are well equipped to do their best job at Apple.\n\nIn short, this position focuses in fostering our North Star and making sure that our vision\nstatement extends across the different design groups: To create, monitor, and maintain high quality flows that enable Apple Silicon to produce chips that enable Apple's best products. You will be working with an energized and highly motivated CAD team that comprehensively supports Apple's chip design efforts.
Minimum of BS degree 10 years of relevant experience\nExpertise in programming in Python, Perl\nKnowledge in Verilog and SystemVerilog\nUnderstanding of Front-End RTL Construction and Analysis workflows
Experience with EDA tools in Clock Domain Crossing, Reset Domain Crossing and Lint\nExcellent communication, debug and root causing skills, including vendor tool problems and vendor management\nPrior customer support experience\nKnowledge of TCL\nExperience in leading large-scale software system development from specification to deployment\nMSEE/CE/CS preferred
As a Front-End Methodology CAD Engineer, you will play a major role in promoting a reliable\nwork environment for developing, maintaining, and improving automation software that design\nteams use for creating, modifying and analyzing RTL. Furthermore, you may support and develop RTL analysis applications like Reset Domain Crossing (RDC), Clock Domain Crossing (CDC), and Lint applications for our SoCs across multiple design sites. In addition, you will have the opportunity to develop Generative AI solutions that the design team can use to improve experience working with these RTL Construction and Analysis applications.\n\nThe Front-End CAD Methodology Engineer plays a key role in promoting and driving robust,\nscalable methodology solutions across RTL Design and DV teams within Apple's HWTech\norganization. You will help ensure the right flows are being used at the right time for project\nmilestones and proper sign-offs are followed through. You will help curate internal training\nmaterials and coordinating vendor trainings so that our Designer/DV engineers are well equipped to do their best job at Apple.\n\nIn short, this position focuses in fostering our North Star and making sure that our vision\nstatement extends across the different design groups: To create, monitor, and maintain high quality flows that enable Apple Silicon to produce chips that enable Apple's best products. You will be working with an energized and highly motivated CAD team that comprehensively supports Apple's chip design efforts.
Minimum of BS degree 10 years of relevant experience\nExpertise in programming in Python, Perl\nKnowledge in Verilog and SystemVerilog\nUnderstanding of Front-End RTL Construction and Analysis workflows
Experience with EDA tools in Clock Domain Crossing, Reset Domain Crossing and Lint\nExcellent communication, debug and root causing skills, including vendor tool problems and vendor management\nPrior customer support experience\nKnowledge of TCL\nExperience in leading large-scale software system development from specification to deployment\nMSEE/CE/CS preferred