What are the responsibilities and job description for the Analog Mixed Signal IP Integration Engineer position at Apple, Inc.?
At Apple, we work every single day to craft products that enrich people's lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a forward-thinking and especially motivated Analog Mixed Signal IP Integration Engineer! As a member of our dynamic group, you will have the rare and great opportunity to work on upcoming products that will delight and encourage millions of Apple's customers every day!
In this highly visible role, you will support the integration of 3rd party IP in the SOCs developed by Apple. Your job is to verify that the IP deliverables are meeting Apple's high quality standards and get flawlessly integrated. The role involves working closely with different cross-functional teams within Apple as well as with external vendors. Occasional travel might be required.
BSEE/MSEE and 7 years industry related experience.
Experience with Verilog modeling and model validation is a plus\nExperience with standards like PCI Express, MIPI, USB or DisplayPort is a plus\nExcellent written and verbal communication skills\nStrong initiative and ownership of responsibilities, productive, able to meet aggressive deadlines\nExperience in RTL design, verification or integration \nDeep knowledge and experience with front-end tools such as simulation, synthesis, lint, logic equivalence, static timing analysis, CDC, RDC, and UPF\nFamiliarity with SOC design flow and verification methodologies\nGood understanding of DFT requirements for SOCs \nExperience writing Verilog, SystemVerilog, SVA hardware description languages
In this highly visible role, you will support the integration of 3rd party IP in the SOCs developed by Apple. Your job is to verify that the IP deliverables are meeting Apple's high quality standards and get flawlessly integrated. The role involves working closely with different cross-functional teams within Apple as well as with external vendors. Occasional travel might be required.
BSEE/MSEE and 7 years industry related experience.
Experience with Verilog modeling and model validation is a plus\nExperience with standards like PCI Express, MIPI, USB or DisplayPort is a plus\nExcellent written and verbal communication skills\nStrong initiative and ownership of responsibilities, productive, able to meet aggressive deadlines\nExperience in RTL design, verification or integration \nDeep knowledge and experience with front-end tools such as simulation, synthesis, lint, logic equivalence, static timing analysis, CDC, RDC, and UPF\nFamiliarity with SOC design flow and verification methodologies\nGood understanding of DFT requirements for SOCs \nExperience writing Verilog, SystemVerilog, SVA hardware description languages