SerDes RTL Design Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

The Role

AMD SerDes Technology team is searching for a passionate and innovative RTL design engineer to develop high-performance, multi-protocol wireline transceivers in state-of-the-art CMOS processes.

 

THE PERSON: 

You have an innovative mindset and a passion for digital design, and verification in general. You are a team player who has excellent communication skills. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

 

KEY RESPONSIBILITIES: 

• Collaborate with system link architects to micro-architect cutting edge high-speed SerDes PHY design
• RTL design of digital blocks, such as calibration and adaptation loops, digital signal processing, clock-data-recovery
• Apply low power design techniques and perform PPA analysis
• Verify intended functionality with block-level test bench
• Run design checker tools such as LINT/CDC/RDC etc.
• Behavioral modeling of custom circuit using Verilog/System Verilog
• Support functional verification and debug of design, and static timing closure
• Collaborate with physical design and validation teams to perform pre-tape out design sign-off and silicon bring-up
  
  
  

PREFERRED EXPERIENCE: 

• Proficient in logic design concepts and RTL coding using Verilog/System Verilog
• Proficient in micro-architecture and developing design specifications
• Proficient with design checker tools and/or functional verification tools
• Knowledge of synthesis flow and static timing analysis
• Knowledge of low power design and methodology
• Experience in design with multiple clock domains
• Experience in mixed signal design
• Experience with Python, Perl, TCL and/or other scripting language
• Experience with SerDes PHY (PMA/PCS) and/or high-speed I/O protocol is preferred
  
  
  

Academic Credentials

• Bachelor's or master’s degree in electrical engineering, computer engineering, or related field
  
  
  

LOCATION: San Jose, CA or anywhere in the US

This role is not eligible for visa sponsorship.

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.