Pre-Silicon Verification Staff Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

The Role

The Infinity Fabric verification team is looking for a senior pre-silicon verification engineer to help verify our configurable switches and die-to-die interconnect. Infinity Fabric is part of every new AMD product being developed across Client, Server, Graphics, and Semi-Custom markets. Our growing team is in need of additional senior engineering experience to help us enhance our configurable testbench and to mentor junior engineers.

THE PERSON: 

The preferred candidate will have proven experience verifying complex design blocks at the IP or SoC level using SystemVerilog/UVM or related technologies. He or she should be comfortable creating and executing on testplans in collaboration with design and verification colleagues in a metric-focused environment.

KEY RESPONSIBILITIES: 

• Develop and enhance SystemVerilog / UVM-based testbenches to verify new features for client, server, graphics, and semi-custom interconnects.
• Interact with architects, RTL designers, performance engineers, and post-silicon validation engineers to develop deep expertise in the Infinity Fabric architecture.
• Estimate the time required to write the new feature tests and any required changes to the test environment
• Build the directed and random verification tests
• Debug test failures to determine the root cause; work with RTL engineers to resolve design defects and correct any test issues 
• Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements
• Mentor junior engineers
  
  
  

PREFERRED EXPERIENCE: 

• Proficient in IP level ASIC verification
• Proficient in debugging RTL code using simulation tools 
• Proficient in using UVM testbenches and working in Linux and Windows environments
• Experienced with Verilog, System Verilog, C, and C   
• Developing UVM based verification frameworks and testbenches, processes and flows
• Good understanding and hands-on experience in the UVM concepts and SystemVerilog language
• Scripting language experience: Perl, Ruby, Makefile, shell preferred.  
• Exposure to leadership or mentorship is an asset
• Interest in driving AI/ML tool adoption for design verification use cases
  
  
  

 ACADEMIC CREDENTIALS: 

• Bachelors or Masters degree in computer engineering/Electrical Engineering
  
  
  

LOCATION:

Santa Clara, CA

This role is not eligible for visa sponsorship.

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.