Methodology Engineer – Static RTL Verification

WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

THE ROLE

This role involves planning, developing, and maintaining AMD EDA tools focused on RTL static checks and supporting frameworks. These tools are used across AMD SoC teams to help ensure high‑quality RTL design.

THE PERSON

You are motivated by solving complex engineering problems and enjoy working with digital design, SystemVerilog, and static RTL checking methodologies. You collaborate effectively with engineers across teams and geographies and are comfortable communicating technical concepts with diverse partners. You approach problems analytically, take ownership of your work, and continuously build new skills.

Key Responsibilities

• Lead and contribute to the development and qualification of a static RTL quality‑checking tool, with a focus on production‑ready quality and scalability
• Collaborate closely with RTL, verification, and methodology teams to integrate the tool into frontend and verification workflows
• Design and execute tool‑qualification regressions across complex AMD SoC designs, ensuring correctness across use cases and configurations
• Build and maintain automation, infrastructure, and reporting to improve regression efficiency and debuggability
• Support frontend, static, and power‑aware design flows, including SystemVerilog, UPF, SDC timing constraints, and static analysis tools (e.g., Lint, CDC, RDC, LEC, VCLP/CLP, Fishtail‑TCM)
  
  
  

Preferred Experience

• Demonstrated experience with RTL lint, CDC, low‑power static analysis, or related verification and design methodologies
• Strong working knowledge of SystemVerilog and UPF
• Proficiency in one or more scripting languages such as Python, Perl, Tcl, or shell
• Experience debugging RTL issues and using static analysis tools
• Familiarity with Linux environments; exposure to Windows is a plus
• Working knowledge of Verilog, SystemVerilog, and/or VHDL
• Experience with industry‑standard static and low‑power vendor tools is beneficial
  
  
  

ACADEMIC CREDENTIALS

• Bachelor’s or master’s degree in Electronics Engineering, Computer Engineering, or equivalent practical experience
  
  
  

This role is not eligible for visa sponsorship.

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.