What are the responsibilities and job description for the EDA Tools & Flows Architect/Developer – AI-Powered Design Automation position at Altera?
Job Details
Job Description:
Job Summary
Altera is seeking a passionate and driven engineer to join our Design Automation team, focusing on developing and enhancing EDA tools, flows, and methodologies for advanced chip design implementation. This role spans digital and custom design domains, including schematic capture, layout automation, and frontend flow development, with a strong emphasis on integrating ML/AI techniques to improve design efficiency and quality.
Key Responsibilities
The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.
$178,900 - $259,000 USD
We use artificial intelligence to screen, assess, or select applicants for the position.
Qualifications
Minimum Qualifications:
Bachelor’s or Master’s degree in electrical engineering, Computer Engineering, Computer Science, or related field (Ph.D. preferred) along with:
Regular
Shift
Shift 1 (United States of America)
Primary Location:
San Jose, California, United States
Additional Locations:
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Job Description:
Job Summary
Altera is seeking a passionate and driven engineer to join our Design Automation team, focusing on developing and enhancing EDA tools, flows, and methodologies for advanced chip design implementation. This role spans digital and custom design domains, including schematic capture, layout automation, and frontend flow development, with a strong emphasis on integrating ML/AI techniques to improve design efficiency and quality.
Key Responsibilities
- Design and architect robust, scalable, and efficient physical design flows covering synthesis, floorplanning, placement, clock tree synthesis (CTS), routing, and signoff.
- Develop and maintain end-to-end design automation flows for RTL-to-GDSII implementation.
- Create and optimize custom schematic and layout flows for analog, mixed-signal, and full-custom digital designs.
- Contribute to frontend design flows, including RTL development, synthesis, linting, clock-domain crossing (CDC) checks, and formal verification.
- Collaborate across teams (design, CAD, and architecture) to identify bottlenecks and deliver automation solutions.
- Leverage ML/AI techniques to improve physical design processes such as placement, routing, timing closure, and power optimization.
- Evaluate and integrate new EDA tools and methodologies to enhance design productivity and quality.
- Develop documentation and training resources to support internal tool adoption and usage.
- Benchmark and validate flow improvements across multiple technology nodes and diverse design styles.
- Work on cutting-edge technologies in chip design and automation.
- Be part of a collaborative and forward-thinking team.
- Opportunity to influence next-generation design methodologies using AI.
The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.
$178,900 - $259,000 USD
We use artificial intelligence to screen, assess, or select applicants for the position.
Qualifications
Minimum Qualifications:
Bachelor’s or Master’s degree in electrical engineering, Computer Engineering, Computer Science, or related field (Ph.D. preferred) along with:
- 10 years of industry experience in EDA tools, flows, and methodologies for ASIC/FPGA design.
- Digital and custom IC design flows, including synthesis, floorplanning, placement, CTS, routing, STA, schematic capture, layout, and signoff (DRC/LVS).
- Frontend design flows (RTL development, synthesis, linting, CDC, formal verification).
- Scripting and automation using Python, Tcl, and EDA tool APIs.
- Hands-on experience with ML/AI techniques and frameworks (TensorFlow, PyTorch, scikit-learn) applied to design automation and optimization.
- Experience in industry-standard EDA tools (Synopsys, Cadence, Siemens/Mentor) and ability to evaluate emerging technologies.
- Demonstrated ability to architect complex flows, drive methodology improvements, and lead cross-functional initiatives.
- Track record of mentoring and influencing technical teams.
- Experience in EDA tool development and automation for physical or custom IC design flows.
- Hands-on expertise with FPGA and ASIC design methodologies, including RTL-to-GDSII implementation.
- Experience with data-driven optimization techniques and reinforcement learning to EDA workflows for performance and efficiency improvements
Regular
Shift
Shift 1 (United States of America)
Primary Location:
San Jose, California, United States
Additional Locations:
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Salary : $178,900 - $259,000