What are the responsibilities and job description for the DSP Design Engineer position at Altera?
Job Details
Job Description:
About Altera
Altera is a global leader in programmable logic solutions, delivering cutting-edge FPGA, SoC FPGA, and software technologies that enable innovation across data centers, communications, automotive, aerospace & defense, and industrial markets. Our engineers tackle some of the most complex design challenges in the semiconductor industry, working at advanced technology nodes to build high-performance, power-efficient solutions used by customers worldwide.
About The Role
The DSP Design Engineer will oversee definition, design, verification, and documentation of state-of-the-art, AI-enhanced DSP IP for next generation FPGA families. Involves analyzing complex DSP topologies and develops parameterizable and efficient IP implementations. Will determine microarchitecture design, logic design, RTL coding, and system simulation. Performs all aspects of the design flow from high level design to synthesis. Oversees physical design place & route, and timing and power model generation. You will be participating in planning and execution of design verification and silicon validation. If you have strong DSP/arithmetic design background, and a passion for cutting-edge silicon development, the Silicon Design Engineering group would love to speak with you!
Responsibilities
The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.
$142,600 - $206,500 USD
We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.
Qualifications
Minimum Qualifications
Regular
Shift
Shift 1 (United States of America)
Primary Location:
San Jose, California, United States
Additional Locations:
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Job Description:
About Altera
Altera is a global leader in programmable logic solutions, delivering cutting-edge FPGA, SoC FPGA, and software technologies that enable innovation across data centers, communications, automotive, aerospace & defense, and industrial markets. Our engineers tackle some of the most complex design challenges in the semiconductor industry, working at advanced technology nodes to build high-performance, power-efficient solutions used by customers worldwide.
About The Role
The DSP Design Engineer will oversee definition, design, verification, and documentation of state-of-the-art, AI-enhanced DSP IP for next generation FPGA families. Involves analyzing complex DSP topologies and develops parameterizable and efficient IP implementations. Will determine microarchitecture design, logic design, RTL coding, and system simulation. Performs all aspects of the design flow from high level design to synthesis. Oversees physical design place & route, and timing and power model generation. You will be participating in planning and execution of design verification and silicon validation. If you have strong DSP/arithmetic design background, and a passion for cutting-edge silicon development, the Silicon Design Engineering group would love to speak with you!
Responsibilities
- Design and implement high-performance DSP IP for next-generation FPGAs
- Contribute to all phases of the design lifecycle including specification development, RTL design, timing closure, power optimization, and design signoff
- Develop and optimize high-speed arithmetic circuits with a focus on performance, power, and area
- Perform datapath synthesis, static timing analysis (STA), and timing closure for advanced process technologies
- Collaborate closely with architecture, verification, physical design, and software teams to ensure robust and scalable solutions
- Support formal verification, logic equivalence checking, and design validation activities
- Participate in design reviews and provide technical leadership and mentorship within the team
The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.
$142,600 - $206,500 USD
We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.
Qualifications
Minimum Qualifications
- Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field and 9 years of hardware design experience on large, complex designs (or 4 years with a PhD), including experience in one or more of the following areas:
- Proven experience in DSP and/or digital communication system datapath design
- Solid working knowledge of DSP and high-speed arithmetic circuit implementation, with a strong theoretical background in this domain
- In-depth knowledge of datapath synthesis, static timing analysis, and timing closure techniques for high-speed designs
- Hands-on experience with STA tools such as PrimeTime, particularly in advanced technology nodes
- Experience with formal verification and logic equivalence checking
- Strong understanding of the full implementation flow including specification, design, timing closure, and power optimization
- Experience with digital design flows including RTL simulation and timing constraints
- Familiarity with ASIC design flows, including libraries, EDA tools, and verification methodologies
- Working knowledge of tools such as PrimeTime, Design Compiler, and place-and-route (PnR) tools
- Strong background in arithmetic operations - fixed point, floating point, and tensor
Regular
Shift
Shift 1 (United States of America)
Primary Location:
San Jose, California, United States
Additional Locations:
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Salary : $142,600 - $206,500