Sr. Manager - CAD EM/IR Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_

Sr. Manager - CAD EM/IR Engineer 

THE ROLE:

As Sr. Manager of the EMIR CAD team, you will manage and technically lead our EMIR CAD team to develop and maintain world-class EMIR flows.  You will collaborate with our internal experts and EDA vendors to plan and drive continuous methodologies improvements, collecting best practices and integrate them into a software designed flow for consistency, efficiency, and ease-of-use.  You will manage your team to provide tools/flows support to the global IP & SoC and 3DIC Stacked Die design teams and work with EDA vendors to resolve tool issues.

THE PERSON:

The ideal candidate is a strong leader with experience leading others in technical and managerial settings.  You have excellent communication and organizational skills, technically strong in EMIR/Totem with knowledge in Physical Design and Advanced Packaging.   

KEY RESPONSIBILITIES:

• Lead a high-performance EMIR CAD engineering team to develop and maintain world-class EMIR flows using state-of-the-art EDA tools (Redhawk_SC, Voltus and Totem)
• Manage the team to providing tools/flows support to the global IP/SoC/3DIC design teams and enable the flow to support new tech nodes
• Collaborate with internal EMIR experts & EDA vendors to drive continuous flow and methodologies improvements
• Work with EDA vendors to resolve tool issues and bugs
• Manage tool versions regression and qualification for deployment
• Motivate and nurture talent

PREFERRED EXPERIENCE:

• 15 years of industrial experience in VLS/silicon design
• Strong technical manager with 5 years of experience managing EMIR flow development & signoff IP, block & SoC level with multiple tape-outs in advanced tech nodes (10nm and below)
• Prior experience working with EDA vendors
• Strong working knowledge in all aspects of Physical Design and Advanced Packaging
• Solid background in VLSI and CMOS fundamentals and electrical engineering knowledge
• Strong analytic and problem-solving skills including the ability to analyze current behavior, identify potential areas for improvement and design of experiments
• Strong mentoring and coaching skills

ACADEMIC CREDENTIALS: 

• Bachelors or Masters degree in Computer/Electrical Engineering 

LOCATION:

• Santa Clara, California, USA

#LI-DD3

At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.