SERDES Design Integration Lead

WHAT YOU DO AT AMD CHANGES EVERYTHING 

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.  Together, we advance your career.  

THE ROLE: 

We are seeking an experienced PMTS-level Analog Macro Integration Lead to own macro- and project-level integration for high-performance ICs. This role combines technical leadership in analog/mixed-signal design with hands-on responsibility for IPCR/Totem/EMIR flows, database/library management, and cross-functional coordination to ensure SOC IP delivery and tapeout readiness.

THE PERSON: 

You have a passion for high speed design with innovative and creative ideas to solve complex design challenges. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. 

KEY RESPONSIBILITIES: 

• Act as the primary technical coordinator for macro-level IP integration and tapeout readiness.
• Coordinate with mid-level block owners to support macro IPCR flows and resolve integration issues.
• Manage IPCR releases and run Totem/EMIR for macro verification.
• Maintain and manage integration databases and library assets required for macros.
• Work closely with AMD CAD and FTO teams to debug and resolve macro-level flow issues.
• Support project-level onboarding and provide SOC IP delivery / tapeout QA.
• Troubleshoot integration problems across layout, CAD, verification, and packaging teams.
• Mentor and guide engineers involved in macro-level integration tasks.
• Strong IC design experience, with significant experience in analog/mixed-signal design and macro-level integration.
• Hands-on experience with Totem and EMIR runs.
• Analog design experience in sub-micron technologies.
• Strong familiarity with Cadence Virtuoso and the Cadence tool suite.
• Proficiency in Unix/Linux environments and scripting (Perl, Python, TCL, or similar).
• Strong organizational skills and the ability to manage multiple concurrent deliverables.
• Excellent interpersonal and communication skills for cross-functional coordination.

PREFERRED EXPERIENCE: 

• ESD design/verification experience.
• Experience debugging CAD flows and interpreting tool log files.
• Experience with database/library management for tapeout flows.
• Prior experience coordinating SOC IP delivery and tapeout QA.

ACADEMIC CREDENTIALS: 

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.

LOCATION: San Jose, CA

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Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.