Senior Design-for-Test (DFT) Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

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THE ROLE:

AMD’s Cores Organization delivers industry leading CPU’s and caches that are the foundation of AMD’s server, client, and gaming business.  We are looking for an experienced VLSI DFT RTL design engineer to join this innovative team.  The candidate will be a key contributor for AMD’s next generation cores and caches, and will join the team based in Fort Collins, CO.

THE PERSON:

The candidate should have strong analytical thinking and problem-solving skills with excellent attention to details.  We work on programs with long timelines, so self-motivation and a commitment to meeting deadlines is required.   We are pushing the envelope on chip performance and manufacture quality, so the status quo must be challenged on every program.  This requires creativity and innovation with excellent verbal and written communication skills.  We work in small teams, and we are part of a large cross-site Core’s organization, so teamwork is vital our success.

KEY RESPONSIBILITIES:

• Collaborate with Cache, CPU, and DFT Architects to design, document, and execute DFT solutions for optimized high-performance Cache and Routing Fabric designs.
• Influence and drive improvements in DFT architecture, MBIST (Memory Built-In Self-Test), and project execution and quality.
• Write and maintain external specifications for product and test teams to use.
• Work closely with the Physical Design team members to drive design closure using experience with Netlist analysis, Static Timing, clock domain crossing (CDC) tools on RTL and gate-level netlists, and Static Power analysis tools and flows.
• Develop ways to improve our CPU design by increasing quality, by simplifying design complexities through innovation, and by improving our technical interactions with other teams.
• Solve design and tool problems requiring ground-breaking approaches and champion innovation across the organization.  Create technical presentations for peers and management.

PREFERRED EXPERIENCE:

• Prior experience with DFT RTL development and pattern delivery, MBIST Architecture, and DFT project execution.
• Strong understanding of DFT concepts in areas of MBIST, IEEE 1149.1 and 1500 standards.
• Working knowledge of multi-clock domain and multi-power domain design.
• Eagerness to learn and grow as a CPU cache array and DFT design engineer.
• Experience collaborating effectively towards the success of a project by working closely with a diverse team across disciplines

ACADEMIC CREDENTIALS:

• BS/MS in EE, CS, CSE (or similar), plus 6 years hardware design experience

LOCATION:

Fort Collins, Colorado, USA

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Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.