Principal Silicon Design Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

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THE ROLE:

The SOC RTG team develops leading edge discrete graphics SOCs. The team owns SOC execution and is actively engaged from architecture to production. Working as part of the SOC leadership team, candidates will gain knowledge in system and IP level design, SOC architecture and implementation strategies.

THE PERSON:

Excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc.  Highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team.

KEY RESPONSIBILITIES:

• Integrate AMD internal IPs RTL/DV environments into SoC
• Debug function/performance of Graphics, Display, SMU IPs
• Engage with IP and SOC teams to drive closure to IP RTL deliverables
• Work with global Front-End design team and physical design team for large scale ASIC chip physical implementation
• Drive design and methodology improvements across teams to improve overall program execution 

PREFERRED EXPERIENCE:

• Proficiency with Verilog/VHDL RTL design languages
• Knowledge of chip bus interfaces such as AHB, AXI and various standard peripherals & interfaces is required
• ASIC DV experience in reusable verification methodology such as UVM
• Have hands-on experience in SOC Design/Integration activities, involving IPs, padring and pinmuxing
• Have knowledge of SOC design specification, architecture and micro-architecture,ASIC, SOC, and IP Verification.
• Strong industry experience in Synthesis, Floor-planning, Placement, clock trees synthesis, Post Route Timing closure for high-speed designs.
• CDC, PTPX, STA, LINT & DFT, IP, Physical design flow & scripting in TCL, Python 

ACADEMIC CREDENTIALS:

• Bachelor or Masters Degree in Electrical Engineering, Computer Engineering or Computer Science

LOCATION: Santa Clara, CA

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Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.