What are the responsibilities and job description for the Principal Reliability Lead Engineer position at Advanced Micro Devices, Inc?
WHAT YOU DO AT AMD CHANGES EVERYTHING
At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.
THE ROLE
As the Reliability Lead, you will serve as the technical authority for extended reliability modeling and silicon-level risk assessment across AMD’s next-generation x86 SoCs. This role is pivotal in ensuring our products meet rigorous reliability standards for automotive, industrial, networking, and edge markets. You will define strategies that safeguard product longevity and performance under diverse operating conditions, influencing design decisions from concept through production.
THE PERSON
We are seeking a reliability expert who thrives at the intersection of hardware and software. You bring deep physics-of-failure knowledge and system-level power and firmware expertise to the table. You will collaborate with architecture, design, and firmware teams to implement aging-aware performance projections, define DVFS policies, and validate models against silicon data. Your ability to anticipate reliability risks and drive mitigation strategies will ensure AMD delivers robust, long-lived solutions that power mission-critical environments.
KEY RESPONSIBILITIES
- Own extended reliability modeling for CPU/APU SoCs across aging modes (BTI, HCI, EM, TDDB).
- Collaborate with architecture and design teams to build aging-aware performance and power projections.
- Define fuse strategies, frequency guard bands, power limits, and DVFS policy guidelines for reliability compliance.
- Partner with firmware teams to implement power management hooks, throttling responses, and mitigation algorithms.
- Validate reliability models using silicon data; drive calibration and refine lifetime projections.
- Correlate models to silicon monitors (PVT, path monitors) and recommend FW/fuse changes for reliability attainment.
- Create cross-functional documentation, risk assessments, and recommendations for leadership and customers.
PREFERRED EXPERIENCE
- MS/PhD in EE/ECE with experience in SoC reliability, product engineering, or device physics.
- Strong understanding of silicon aging models, derating, and reliability qualification standards (AEC-Q100, JEDEC).
- Expertise in power delivery (SI/PI), IR-drop, EDC/TDC, clock/power gating; experience with reliability telemetry/PVT monitors.
- Proven ability to influence FW architecture (power/thermal/idle governors) and fusing/DFX policies.
- Strong data analysis skills (Python/SQL) and dashboarding for reliability tracking.
- Automotive/industrial reliability standards (AEC-Q100, ASIL), field-reliability analytics, and silicon lifecycle management experience are a big plus.
ACADEMIC CREDENTIALS
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
LOCATION:
Austin, TX
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