Hardware Development Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

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THE ROLE:

As a Hardware Development Engineer, you will analyze existing design blocks for faults and vulnerabilities. Design and specify the micro-architecture for future SOC (system on chip) blocks with the necessary infrastructure and architecture for power and performance area PPA and design for testing DFT including the Functional Safety Requirements.

THE PERSON:

The ideal candidate will have the ability to organize and present complex technical information. Strong written and verbal communication. 

RESPONSIBILITIES:

• RTL design and debug of functions in Verilog / System Verilog
• Integration of hard macro or soft RTL IP into SOC top level
• Power domain/island creation (with UPF)
• Execution of quality checks to improve quality of RTL/UPF/SDC deliverables
• Analysis of design metrics and making implementation choices to optimize PPA (power performance area)
• Targeting SOC RTL to process technology
• Facilitating DFx/MBIST instrumentation
• Floor-planning and partitioning
• Work with verification and physical design teams to achieve high quality design and successful tape out
• Collaborate with cross-functional teams to solve novel problems across multiple functional areas
• Design and implement underlying Power Management, Clk/Rst, NOC (network on chip) and DFT (design for testing) infrastructures to ensure implementation tool requirements are met and are optimized for compile time and memory
• Chip level Functional Safety analyses such as FMEDA and DFA
• Participate in tape out checklists and reviews
• Build automation (Python, TCL, Perl) to enhance productivity of self and team
• Digital design and experience with RTL design in Verilog/System Verilog
• Solid understanding of DFT technologies and some experience with execution of DFT flows
• Experience with SOC tools including Spyglass, Questa CDC, Cadence Conformal, VCS simulation
• Experience in specifying timing constraints with several clock domains and modes

PREFERRED EXPERIENCE:

• Basic experience with Synopsys Design Compiler and Primetime
• Experience designing with multiple power domains and islands using UPF
• TCL, Python, Perl scripting
• Version control systems such as Perforce, IC Manage or Git
• Understanding of FPGA architecture and implementation flow
• Fluent in working with Linux environment

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Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.