DC-GPU Power Performance Attainment Manager

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THE ROLE: 

AMD’s Datacenter Performance Group is seeking a Technical Manager for the PPA leadership team driving the Power Constrained Performance of our industry-leading AI/ML/HPC GPUs. The role will involve providing leadership and management of a small team of experienced PPA leads who drive many aspects of Perf@Power attainment, including pre-Si power modeling, post-Si correlation, workload analysis, setting PPA targets and driving attainment, power/perf roll-ups and reporting, methodology innovations and development.

THE PERSON: 

The ideal candidate has experience leading others in technical and managerial settings. You also have excellent communication, writing, and presentation skills.  Being passionate about performance and power efficiency, and managing engineers is a key ingredient for success in this role.

KEY RESPONSIBILITIES: 

• Manage a small team of PPA leads, provide technical guidance and direction on PPA modeling, projections and attainment for AMD Instinct AI/ML/HPC accelerators.
• Work with business unit and product architecture to define product configurations, capabilities and targets.
• Own power-constrained performance modeling, projections, implementation target setting and attainment tracking from Concept-exit (pre-si) to Product launch (post-si).
• Cross functionally lead PPA attainment by working with various engineering functions including SOC architecture, System Design, IP Design, Circuit Design, Foundry team, CAD, Physical Design, Software, Power Management, Post-si validation.
• Develop skillsets and methodologies in the team for important PPA domains like Power Modeling at various stages of SoC development, Cdyn/Leakage/STA/Area trade-offs and attainment, Silicon Power/Performance debug, Post Si calibration of models, Work-load power analysis.
• Roll-up Power/Performance readouts, present in executive forums, motivate cross-functional teams on power efficiency improvements.

KEY QUALIFICATIONS: 

• A good mix of management and technical expertise
• Experience (and interest in) managing a team of senior engineers who are experts in PPA
• Fluency in communicating with various engineering teams, business leads and executive management
• Background in Computer Architecture, Processor/Accelerator development
• Experience in Power/Performance projections, modeling and optimization at SoC or System level
• Familiarity with digital logic physical design and power management techniques (clock gating, power gating, V-F curves, p-states, on-die voltage regulation, clock integrity, etc..)
• Familiarity with post-silicon power/performance debug, model correlation
• Knowledge of DL/ML/LLM workloads will be a bonus

ACADEMIC CREDENTIALS: 

• Bachelor's or Master's degree in computer engineering/Electrical Engineering preferred.

LOCATION: Santa Clara, Ca; Austin, Tx, Ft. Collins, Co could be options as well. 

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Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.