Analog Design Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

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THE ROLE:

We are searching for a senior AMS circuit architect to join the GDDR PHY System architecture team.  This is an exciting opportunity to be a member of the Memory IO design team responsible for defining, specifying, and driving circuit architecture for High-speed IO on advanced technologies for future generations of AMD’s graphics, Data center and semi-custom products.

THE ORGANIZATION:
The system architecture organization is responsible for developing and driving systems for Memory connectivity. The organization drives over-all system optimization through detailed specifications for DRAM and GPU to meet memory bandwidth, energy scaling and area.  We are responsible for driving Serdes circuit topologies and architecture to meet or exceed system specifications. Work with SOC and DRAM Vendors to enable optimized systems and standards.

THE PERSON:

• Knowledge of high-speed analog design techniques for Serdes, GDDR, HBM, D2D
• Good knowledge of Higher order modulations (PAM3/4), Equalizers like CTLE, DFE, Adaptation
• Strong working knowledge of FinFet technologies and their challenges
• Excellent analytical and problem-solving skills along with attention to details
• Must be a self-starter, able to drive tasks independently and efficiently to completion
• Strong/effective communication skills
• Enthusiastic team-first mentality
• Ability to provide mentorship and guidance to junior engineers
• Relevant academic background (PhD preferred) and at least 5 years’ progressive experience

KEY RESPONSIBILITIES:

• Drive circuit architecture for high-speed analog functions to achieve high energy efficiency
• Design/implement various state-of-the-art, high-speed (32 Gbps, PAM3/PAM4) analog/mixed-signal blocks for GDDR and other SerDes PHYs
• Deliver detailed specifications & documentation
• Develop circuit schematics and work closely with circuit and layout teams to drive designs to completion (including physical verification and backend/reliability flows)
• Engage with cross disciplines (e.g. Firmware, Design Verification, SOC Architects) to ensure successful and high-quality execution

ACADEMIC CREDENTIALS:

• Bachelors/ Masters/ PhD preferred

LOCATION:  Santa Clara, CA ( open to other AMD locations)

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Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.