SoC DV Engineer

We are looking for a Senior SoC Design Verification Engineer - responsible for developing the verification environment, testbench components, firmware-driven testing, and infrastructure for a next-generation mixed-signal SoC. The engineer will lead development of new BFMs, porting of existing testbench components, creating test suites, enabling automated regressions, and driving coverage closure across digital-analog interfaces, SPI flash flows, and new cross-chip communication protocols.

• Testbench Architecture & Development
• Upgrade and enhance the Digital Analog Model to support MSIC-specific analog array size, new DAC control features, and programming behavior.
• Develop compile/load flows for Quad-SPI Flash using vendor models (e.g., Winbond), including make file updates and per-test case memory image generation.
• Architect and implement the Controller BFM, enabling single/burst R/W transactions, protocol checking, and full integration into the verification environment.
• Evaluate, develop, and BFM based on updated design requirements.
• Update JTAG access modules to support expanded TAP chains, multi-TAP routing, and ARM DAP interactions.
• Maintain and reuse / port UART capture/display modules for firmware printf/debug use-cases.
  Required Skills & Experience
  8-12 years of experience in SoC Verification with strong proficiency in:
• Verilog-HDL
• C test development at SoC level
• SV Assertions
• TCL/Python/Shell scripting
• Experience with:
• Protocol Knowledge (JTAG, SPI, UART, serial communication protocols and AMBA APB, AHB interconnect protocols)
• Gate-level simulation & SDF flows
• Coverage tools and methodologies (functional code coverage)
• Hands-on experience debugging complex SoC issues involving ARM subsystems.
  Preferred Qualifications
• Prior work on mixed-signal or digital-analog interface verification.
• Understanding of AHB/APB/AXI interconnects.
• Exposure to version control like GitHub Actions, Jenkins, or similar.

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