What are the responsibilities and job description for the Senior Post-Silicon Validation Engineer position at ACL Digital?
We’re looking for a highly skilled Post-Silicon Debug Engineer to lead silicon bring-up and failure analysis efforts in a fast-paced, collaborative environment.
This is a hands-on role focused on identifying, analyzing, and resolving silicon failures across functional and stress test modes.
What You’ll Do
Lead post-silicon debug across functional and stress test modes to root-cause silicon failures
Perform shmoo analysis, voltage/frequency margining, and parametric sweeps to identify failure boundaries
Debug complex issues involving:
- CDC paths
- Clocking behavior
- Resets
- Signal integrity
Collect, organize, and correlate large silicon datasets to identify systematic failure trends
Partner closely with design, validation, and test teams to drive silicon fixes and implement effective workarounds
What We’re Looking For
Proven experience in post-silicon debug and silicon bring-up
Strong expertise in:
- Failure analysis
- Shmoo characterization
- Voltage and frequency margining
- Parametric analysis
Deep understanding of:
- CDC (Clock Domain Crossing) paths
- Clocking architectures
- Reset design and behavior
- Signal integrity fundamentals
Ability to analyze and interpret large silicon datasets to uncover systematic issues
Collaborative mindset with experience working cross-functionally with design, validation, and test engineering teams