What are the responsibilities and job description for the Senior Physical Design Engineer position at ACL Digital?
- Strong experience in RTL synthesis (Cadence Genus / Fusion Compiler) with SDC constraints and QoR optimization
- Hands-on Static Timing Analysis (Tempus): setup/hold closure, MMMC, OCV, timing signoff
- Ability to debug and close timing issues across synthesis and floorplanning stages
- Experience in block-level floorplanning (Innovus/Fusion Compiler): macro placement, IO planning, utilization
- Exposure to advanced nodes (5nm or below)