What are the responsibilities and job description for the Mixed-Signal Design Verification Engineer position at ACL Digital?
We are looking for a Design Verification Engineer to work on high-speed PHY and mixed-signal IPs
Responsibilities:
- Build verification environments using SystemVerilog / UVM
- Perform PHY-level, mixed-signal, low-power, formal, and gate-level verification
- Write SVA assertions, functional coverage, and drive coverage closure
- Collaborate with digital, analog, SoC, and post-silicon teams
Requirements:
- Strong experience in SystemVerilog / UVM
- Experience with PHY / SerDes or mixed-signal IP verification
- Experience in protocols: PCIe, USB, MIPI, DDR, CXL, UFS
- Experience with PLL, ADC, DAC, sensors
- Experience range: 4 years to 15 years