ASIC / SoC Engineer – Low Power

Job Title: ASIC / SoC Low Power Engineer (UPF, Conformal Low Power)

Location: San Diego, CA (Onsite)

Job Type: Contract

Pay range: $47.00 - $58.00/hr on W2 (all inclusive)

Responsibilities:

• Perform SoC-level low power implementation for ASIC designs.
• Define and validate power intent using UPF (Unified Power Format).
• Run low power checks using Cadence Conformal Low Power (CLP) or similar tools.
• Implement power optimization techniques (clock gating, power gating, isolation, retention).
• Collaborate with RTL, DFT, Design Verification, Synthesis, and Physical Design teams.
• Support integration of digital and mixed-signal SoC components.

Required Skills:

• Experience in ASIC / SoC design and development.
• Strong knowledge of low power methodologies.
• Hands-on experience with UPF.
• Experience with low power verification tools (CLP preferred).
• Understanding of full SoC design flow (RTL to GDSII).