MTS - Compiler Engineer

Compiler Engineer — Backend

Mountain View, CA

About the Role

An early-stage AI hardware company is seeking a Compiler Engineer to develop the backend compiler infrastructure for a custom accelerator architecture.

You will own core backend functionality across instruction selection, register allocation, scheduling, code generation, and binary tooling. This role sits at the intersection of compilers, computer architecture, and silicon, with direct influence over how software maps onto the underlying hardware.

You will work closely with architecture, chip design, runtime, and systems teams to bring up the compiler stack, improve generated-code quality, and support the platform from early development through production deployment.

What You’ll Do

• Develop and maintain a compiler backend for a custom accelerator instruction set.
• Implement instruction selection, register allocation, instruction scheduling, lowering, and code generation.
• Support scalar, vector, and floating-point execution pipelines.
• Build and maintain target descriptions, machine models, and backend infrastructure.
• Contribute to assembler, linker, loader, and binary-format support where needed.
• Debug correctness issues and performance regressions across the full compilation flow.
• Analyze generated code and improve code quality, throughput, latency, and hardware utilization.
• Partner with hardware architects on ISA design and compiler-hardware co-design.
• Support early architecture bring-up and validation using simulation, emulation, or pre-silicon environments.
• Develop automation and assisted tool flows to accelerate compiler development, testing, and performance tuning.
• Collaborate with frontend, middle-end, runtime, kernel, and systems engineers.

What We’re Looking For

• 5 years of compiler engineering experience.
• Hands-on experience developing or extending an LLVM target backend.
• Deep understanding of LLVM backend internals, including:
• TableGen
• Instruction selection
• Register allocation
• Instruction scheduling
• Machine IR
• Target lowering
• Code emission
• Strong knowledge of computer architecture and instruction-set design.
• Experience reasoning about scalar, vector, floating-point, or accelerator execution pipelines.
• Ability to debug compiler correctness issues across multiple compilation stages.
• Experience identifying and resolving generated-code performance regressions.
• Strong C programming skills.
• Ability to work effectively across compiler, architecture, hardware, and systems teams.

Preferred Experience

• Custom ISA or new-target bring-up.
• MLIR or other intermediate-representation frameworks.
• GPU, NPU, DSP, or accelerator compiler backends.
• Linker, loader, assembler, object-file, or binary-tooling development.
• RISC-V, ARM, x86, or another modern instruction-set architecture.
• Runtime or driver integration.
• Architectural simulators, emulators, or pre-silicon development environments.
• Hardware-software co-design.
• Performance analysis and compiler optimization for AI or high-performance computing workloads.

Relevant Keywords

Compiler Engineer, LLVM, LLVM Backend, LLVM Target Backend, Backend Compiler, Code Generation, CodeGen, TableGen, SelectionDAG, GlobalISel, Instruction Selection, Register Allocation, Instruction Scheduling, Machine IR, MIR, Target Lowering, Target Description, Machine Instructions, MC Layer, Assembler, Linker, Loader, Object Files, ELF, Relocations, Custom ISA, ISA Design, Compiler Bring-Up, New Target Bring-Up, Scalar Pipelines, Vector Pipelines, Floating-Point Pipelines, SIMD, VLIW, RISC-V, ARM, x86, GPU Compiler, NPU Compiler, Accelerator Compiler, MLIR, LLVM IR, C , Compiler Optimization, Generated Code Quality, Performance Tuning, Correctness Debugging, Compiler Regressions, Runtime Integration, Driver Integration, Architectural Simulation, Hardware-Software Co-Design, Computer Architecture, Member of Technical Staff, MTS, PMTS, Principal Member of Technical Staff